Semiconductor memory devices include volatile memory devices that lose their data when their power is turned off and non-volatile memory devices, which retain data when their power is turned off. Non-volatile memory devices may be classified as read only memory (ROM) devices, on which stored data is permanent and cannot be modified once the device is fabricated. Another type of non-volatile memory device is an electrically erasable programmable read only memory (EEPROM), which enables data to be programmed on a byte by byte basis. One example of an EEPROM is a flash memory device, on which data may be erased and reprogrammed.
As is known, EEPROM devices are structured to include a source/drain and a gate electrode. The gate electrode has a layered structure including a gate insulating film, a floating gate, a dielectric film and a control gate. The gate insulating film typically consists of a gate oxide film and a tunnel oxide film, which is thinly formed between the floating gate and the drain to enable tunneling of electrons.
During operation, EEPROMs typically provide a program mode in which the floating gate is charged with electrons to put the memory cell in a conducting state. In an erase mode the floating gate is discharged to put the memory cell in a non-conducting state. The program mode is achieved by applying high voltage to the control gate. Electrons are moved from a conduction band of the drain through the thin tunnel oxide film to the floating gate by the applied voltage. The electrons arriving at the floating gate are captured by shutting off the applied voltage. As a result, the electrons accumulated in the floating gate form a P-channel and generate a low threshold voltage. At that time, the tunnel oxide film is not only used as the gate oxide film of the memory cell, but is also used as a potential barrier for the electrons accumulated in the floating gate, thereby exerting a substantial effect upon an electric charge retaining characteristic of the floating gate.
A layout of a conventional EEPROM is described with reference to FIG. 1. As shown in FIG. 1, a plurality of impurity-doped regions used as the source/drain are arranged and spaced apart from each other at regular intervals on a desired portion of a silicon substrate.
On a semiconductor substrate 100 in which an impurity-doped region 101 is not formed, a plurality of control gates 103 are spaced in parallel apart from each other in a horizontal direction, i.e., in a width direction of a channel. A desired shape floating gate having a desired shape is positioned apart from a floating gate 102 of an adjacent cell between the control gate 103 and an upper portion of the substrate in the impurity-doped regions 101 spaced apart from in a vertical direction to the substrate 100, i.e., in a longitudinal direction of a channel.
In production of an EEPROM device, as well as conventional devices, the gate insulating film is formed on the semiconductor substrate comprising the impurity-doped region by a chemical vapor deposition, before forming the floating gate 102 and the control gate 103. Growth speed of the gate insulating film in the impurity-doped region is different from that of the gate insulating film in the region that is not impurity-doped, thereby destabilizing characteristics of the device.
A conventional method of manufacturing the gate insulating film of the EEPROM is described below. First, a screen oxide film is formed on the semiconductor substrate having a device isolating film using a low pressure chemical vapor deposition to protect the semiconductor substrate. At that time, the screen oxide film is deposited in a thickness of 40 to 60 Å under a temperature of 700 to 900° C. In turn, a photoresist film pattern is formed on an upper portion of the screen oxide film to define a gate insulating film forming region, and impurity ions are implanted onto the entire surface of the semiconductor substrate comprising the photoresist film pattern. At that time, impurity ion implantation is performed via a first ion implantation and a second ion implantation. The first ion implantation is performed by implanting 31P ions using a high current ion implanter, wherein the ion implantation energy is 10 to 25 KeV and the ion dose is 3 to 7×1013 ion/cm2. Then, the second ion implantation is performed by use of 75As ions, wherein the ion implantation energy is 30 to 50 KeV and the dose is 1 to 3×1013 ion/cm2. As a result of performing the impurity ion implantation, the impurity ion is not implanted in the semiconductor substrate in which the photoresist pattern is formed.
After completing the impurity ion implantation, the semiconductor substrate is annealed to induce dispersion of the ions, thereby forming an impurity ion region corresponding to the source/drain region. Then, the photoresist film pattern and the screen oxide are removed.
The gate insulating film is formed with the photoresist film pattern and the screen oxide is removed. The gate insulating film generally consists of a double layer, i.e., a gate oxide film and a tunnel oxide film. The gate oxide film and the tunnel oxide film are sequentially formed to form the gate insulating film.
The gate oxide film is formed to have a thickness of about 200 Å under a temperature of about 800° C. At that time, growth speed of the gate oxide film in the impurity-doped region is different from that of the gate oxide film in the impurity-undoped region (i.e., the region that is not impurity-doped). As shown below in Table 1, which is a result obtained from a test carried out under the above conditions, when the gate oxide film is formed at a temperature of 800° C. using a process time of 32.5 minutes, a gate oxide film of 1364.8 Å is grown in the impurity-doped region, while the gate oxide film of 197.4 Å is grown in the impurity-undoped region. Because the growth speed of the gate oxide film in the impurity-doped region is different from that of the gate oxide film in the impurity-undoped region, imbalanced or different heights result at the formation of device patterns such as a floating gate, a control gate or the like, thereby degrading the reliability of the device.
TABLE 1GrowthProcessThickness(Å)Time(Min)Impurity Ion Region1364.832.5Remaining Region197.432.5